The present invention relates to a semiconductor integrated circuit having a gate array structure in which leakage currents can be reduced in a gate array or an embedded cell array, which is a kind of the gate array.
In recent years, increases in speed and degree of integration of semiconductor integrated circuits have advanced by development of fine pattern techniques. In such semiconductor integrated circuits, reduction in power dissipation poses one great problem. For example, in semiconductor integrated circuits, such as a gate array formed by spreading a large number of transistors all over, and an embedded cell array (hereafter abbreviated to ECA) which is a cell base semiconductor integrated circuit formed by embedding gate arrays as large scale macros, gate lengths of transistors are becoming smaller. This results in a problem of increased leakage currents and consequent increased power dissipation.
That is, owing to finer smaller gate length, it becomes possible to perform operation fast and also it becomes possible to use many transistors, resulting in a high degree of intergration. On the other hand, the length of isolation transistors which isolate adjacent transistors from each other and of isolation transistors which isolate cells from each other in the cell array scheme is made smaller. As a result, the leakage current tends to increase and power dissipation tends to increase. On the other hand, the length of isolation transistors which isolate adjacent transistors from each other and of isolation transistors which isolate cells from each other in the cell array scheme is made finer. As a result, the leak current tends to increase and power dissipation tends to increase.
Especially in semiconductor integrated circuits such as those used in portable devices, the increase in power dissipation directly affects the battery life, and poses a very serious problem.
FIG. 10 shows an example of a conventional typical ECA cell. In this figure, reference numeral 1 denotes a power supply wiring section, 2 a ground wiring section, 3 a signal wiring section, 4 an isolation transistor, 5 a PMOS transistor region, and 6 an NMOS transistor region. Reference signs A, B and C denote positions in the ECA cell. That is, 4A denotes an isolation transistor 4 located in the position A, and 4B an isolation transistor 4, located in the position B. The isolation transistor 4 is a transistor which is always held in the off-state by connecting a PMOS transistor at its gate to the power supply wiring section 1 or connecting an NMOS transistor at its gate to the ground wiring section 2, and which thereby functions to electrically isolate right and left active areas from each other.
FIG. 11 is a circuit diagram which shows the ECA cell of FIG. 10. A NOR circuit is located between the positions A and C. An inverter circuit is located between the positions C and B. As a whole, the cell forms an OR cell. Fl and F2 denote input terminals of the two-input NOR circuit, and G denotes an output terminal of an extra-cell gate in the OR cell. An output terminal of an intra-cell gate is supplied to a node E. Intra-cell gates indicate circuits, each of which is independent and has an individual function, within a cell having some function as a whole. The cell as a whole is the OR cell located between the positions A and B. The NOR circuit located between the positions A and C, and the inverter circuit located between the positions C and B correspond to the intra-cell gates, respectively. Each of the individual independent circuit units may be a logic circuit or a sequence circuit.
In FIG. 11, if the signal at the node E is at high logical level (xe2x80x9cHxe2x80x9d), there is no problem in particular. If the signal is at low logical level (xe2x80x9cLxe2x80x9d), however, a leak current occurs from the intra-cell power supply wiring section 1 through the PMOS isolation transistor 4C in a direction indicated by an arrow, posing a problem.
FIG. 12 shows an example of a state between cells in conventional typical ECA cells. In this figure, the same characters are assigned to the components corresponding to those in FIG. 10. When conventionally designing the arrangement of adjacent cells 1 and 2, isolation transistors 4 at ends of respective cells are overlapped in order to increase the degree of integration.
FIG. 13 is a circuit diagram which shows a section between ECA cells shown in FIG. 12, in which OR cells are disposed adjacently. F1 and F2 denote input terminals of the cell 2, and G denotes an output terminal of an extra-cell gate of the cell 1. If the signal at the output terminal of the extra-cell gate is H, then a leak current flows to a ground wiring section 2 through an NMOS isolation transistor 4B. If the signal at the output terminal G of the extra-cell gate is L, then a leak current flows from the power supply wiring section 1 located outside the cell through a PMOS isolation transistor 4A in a direction of an arrow, posing a problem.
It is an object of the present invention to provide a semiconductor integrated circuit of a gate array structure with which reduction in power dissipation has been achieved while coping with the finer gate length. Herein, the semiconductor integrated circuit of gate array structure is a concept including an embedded array block (EAB) or an embedded cell array (ECA), not to speak of a gate array.
The semiconductor integrated circuit of gate array structure according to one aspect of the present invention, comprises an intra-cell gate output section, an intra-cell power supply wiring section, and a plurality of isolation transistors disposed in series between the intra-cell gate output section and the intra-cell power supply wiring section.
The semiconductor integrated circuit of gate array structure according to another aspect of this invention, comprises an intra-cell gate output section, an intra-cell ground wiring section, and a plurality of isolation transistors disposed in series between the intra-cell gate output section and the intra-cell ground wiring section.
The semiconductor integrated circuit of gate array structure according to still another aspect of the present invention, comprises an intra-cell gate output section, an intra-cell first power supply wiring section, and a plurality of first isolation transistors disposed in series between the intra-cell gate output section and the intra-cell first power supply wiring section. This semiconductor integrated circuit also comprises an intra-cell second power supply wiring section and a plurality of second isolation transistors disposed in series between the intra-cell gate output section and the intra-cell second power supply wiring section.
The semiconductor integrated circuit of gate array structure according to still another aspect of the present invention, comprises an extra-cell gate output section, an extra-cell power supply wiring section in an adjacent cell, and a plurality of isolation transistors disposed in series between the extra-cell gate output section and the extra-cell power supply wiring section in the adjacent cell.
The semiconductor integrated circuit of gate array structure according to still another aspect of the present invention, comprises an extra-cell gate output section, an extra-cell ground wiring section in an adjacent cell, and a plurality of isolation transistors disposed in series between the extra-cell gate output section and the extra-cell ground wiring section in the adjacent cell.
The semiconductor integrated circuit of gate array structure according to still another aspect of the present invention, comprises an extra-cell gate output section, an extra-cell first power supply wiring section in an adjacent cell, and a plurality of first isolation transistors disposed in series between the extra-cell gate output section and the extra-cell first power supply wiring section in the adjacent cell. The semiconductor integrated circuit also comprises an extra-cell second power supply wiring section in the adjacent cell and a plurality of second isolation transistors disposed in series between the extra-cell gate output section and the extra-cell second power supply wiring section in the adjacent cell.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.